HIGH-SPEED, AREA-EFFICIENT, RECONFIGURABLE, FINITE IMPULSE RESPONSE (FIR) DIGITAL FILTER
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Max. FIR order 32 I/O word length 16-bit Technology 1.2m CMOS Coef. word length 16-bit Core Area 4.2 x 2.8 mm2 Max. data rate 175MHz Die size (with pads) 5.9 x 3.4 mm2 Num. of pins 84This chip represents a significant improvement in area efficiency (thus cost) over other competitive chips while still being capable of processing data generated with today's high speed A/D converters. Applications, in addition to filters and correlators, include Hilbert transforms, signal conditioning, and channel equalization for HDTV, satellite and other wireless communications systems, disk drives, radar and sonar, spectrum analysis, digital test equipment, etc. The chip is also ideal for rapid system prototyping. Due to its high area efficiency, this chip provides an alternative to custom FIR filter ASICs, with advantages that are similar to those of FPGAs (i.e., is a standard reconfigurable circuit that readily allows for design changes). Since the core of the chip is generated by a silicon compiler, it also can be used as a block embedded in a larger system chip where the size (prototype=32 tap max.) and wordlength (prototype=16 bit) can be revised to meet arbitrary requirements. The current prototype can easily be re-optimized for operation at higher or lower speed and filter design software is available to select optumim filter coeffients and hardware allocations.
| Reference: UCLA Case No. 1993-508 | US Patent Number: 5,479,363 |
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