BACKGROUND:  The ever shrinking circuit dimensions mandates an increasing demand to control the critical dimension of device and interconnect structures. As the feature size of upcoming processes reduces, sidewall roughness plays an even more important role in the performance of integrated circuits. Particularly, line edge roughness (LER) and line width roughness (LWR) need to be eliminated. However, current techniques proposed for reducing roughness-associated damages result in only marginal improvements.

INNOVATION:  Researchers at UCLA have developed a method that simultaneously eliminates both the short and long range roughness on device sidewalls. Through employing orientation-dependent crystallographic wet etching, atomically flat sidewalls are fabricated and transferred to any desirable orientation for device fabrication. As a result, the method eliminates (not only reduces) the LER and LWR issue, resulting in high performance transistors and integrated circuits.

POTENTIAL APPLICATIONS 

• Semiconductor manufacturing industry for high performance integrated circuits

ADVANTAGES

• LER and LWR free features
• Atomically flat surface with arbitrary orientation
• Compatible with various device substrates

Reference: UCLA Case No. 2010-002