BACKGROUND:  Much like other circuit types, there is a never-ending demand for better, faster, more power efficient FPGAs. However, as the complexity of FPGA architectures increase, device sizes shrink, and process variations widen, it becomes increasing difficult to meet the demand for improvement. For these same reasons, other problems such as soft error rate (SER) become more pronounced and more difficult to correct. Therefore, it is almost imperative for FPGA designers to make use of the most advanced, state-of-the-art software tools and algorithms. The algorithms disclosed here allow FPGA designers to meet the demand for continued improvement in FPGA performance.

INNOVATION 

The invention includes three major components:

• both deterministic and stochastic time budgeting to reduce power without preformance loss for perperformance ASICs and FPGAs.
• a stochastic or chipwise FPGA synthesis flow including clustering, placement and routing to improve FPGA performance and reduce power with presence of process variations and pre-routing interconnect uncertainty.
• the trace-based methodologies to collect traces on logic probability and sensitivity and are used for concurrent device and architecture optimization.

POTENTIAL APPLICATIONS 

• FPGA and ASIC design

ADVANTAGES

• Improved FPGA performance
• Reduced FPGA power consumption for a given level of FPGA performance
• Improved product yield
• Shorter design cycles

DEVELOPMENT-TO-DATE:  The invention has been implemented in software and verified by detailed simulation.

Reference: UCLA Case No. 2008-129