BACKGROUND:  Si technology involves electrical gates and contacts having nanoscale thickness and width. Copper is commonly used for interconnect wires in Si technology. When reduced to nanoscale thickness (e.g., 50 nanometers), copper can sag under the influence of gravity, affecting the orientation of the interconnect wires. This creates interference between the wires, and degrades the performance of the Si technology.

INNOVATION:  The novel material involves specially treating copper (Cu) to produce patterned irregularities to obtain nano-twinned copper thin films. Nano-twinned Cu is an ideal material for Si interconnects because it is ten times stronger than untreated Cu, and retains all of the electrical conductivity of untreated Cu. The material therefore improves Si technology performance by minimizing electrical interference caused by interconnects.

POTENTIAL APPLICATIONS 

• Large-scale-integration of interconnect structures on Si
• Transistor interconnects
• Free standing Cu interconnects with air as a dielectric medium
• Flip chip joint technology
• Under-bump-metallurgy (UBM)
• Microelectronics

ADVANTAGES

• Combines ultra-high mechanical strength and undiminished electrical conductivity
• Enables rapid application of nanoscale material in the microelectronics industry
• Improves the performance of Si technology interconnects

DEVELOPMENT-TO-DATE:  The novel technology has been successfully fabricated and verified.

Reference: UCLA Case No. 2007-005