BACKGROUND:  Volatile memory architectures, such as SRAM and DRAM, are high-speed but consume significant power while in use. When powered off, volatile memory architectures lose the ability to retain information, which must be transferred to low-speed, non-volatile memory storage prior to powering down. The transfer causes delays and consumes further power. Furthermore, traditional non-volatile memories operate at voltages different from those of volatile memories, complicating their integration on the same circuit.

INNOVATION:  The novel memory architecture integrates volatile and non-volatile memory technologies on the same circuit, offering greater efficiency and flexibility. High speed performance and lower total power consumption are achieved, and the system ensures that critical data is retained during changes in or loss of system power. An active power management system achieves benefits autonomously, such that it appears to the user that the high-speed volatile memory is always in use. Thus, the benefits of volatile memory are realized without any noticeable degradation in system performance, while avoiding the drawback of losing data when powered off.

POTENTIAL APPLICATIONS 

• Mobile computing systems and electronic devices with extended battery life.
• Encryption schemes, authentication circuits, adaptive equalizers, convolutional encoders, pseudorandom noise generators, and adaptive filtering arithmetic coding systems.
• Quality of service improvement and storage of multimedia bit streams such as digital radio and digital video, as well as video encoding.
• Template matching, target recognition, motion compensation for video compression, and recognition-based search algorithms.
• Video game systems and music players.

ADVANTAGES

• Reduces overall device power consumption and prolongs battery life.
• Augments conventional architectures with integrated, embedded non-volatile memory.
• Provides a way to store mission critical data independently of the power supply.
• Records digital file modifications rapidly without needing to commit changes to slower media such as hard drives.
• Enables operation at a layer of abstraction below the application level.
• Integrates volatile and non-volatile memory devices, and processing circuitry, on a single chip.

DEVELOPMENT-TO-DATE:  The technique has been successfully tested and confirmed.

Reference: UCLA Case No. 2006-333

US Patent Application: 20060227605