BACKGROUND:  Circuit densities have shown continued increases over the years, as technology improvements allow for more circuitry per unit area of microchip. Known technologies for implementing chip circuits include very large scale integration (VLSI) on Si or silicon-on-insulator (SOI) wafers. However, these approaches for increasing density are constrained by the inherent limitations of wafer-based technologies.

INNOVATION:  The novel technology represents the next stage in circuit density advancement, in the form of large scale integration of MOSFET devices on a Si nanowire. Utilizing nanowire constructions, and/or a parallel array of nanowire structures, enables device properties that are different from and unique compared to VLSI integration on SOI or Si wafers.

POTENTIAL APPLICATIONS 

• Very large scale integration of transistor circuits on Si nanowire array.
• Unique configurations including multiple transistors connected in serial and in parallel.
• Dynamic random-access memory (DRAM) chips.

ADVANTAGES

• Provides word and bit lines for a Si nanowire transistor array structure.
• Enables selective measurement of the source-to-drain current of one or multiple transistors simultaneously.
• Enables random access to any and/or all transistors in the 2-dimensional array.
• Enables connection of multiple transistors in serial and parallel.
• Integrates MOSFET devices in Si nanowires.

Reference: UCLA Case No. 2006-219