BACKGROUND:  Modern VLSI designs see a large impact from process variation as devices scale down to nanometer technologies. Not surprisingly, process variations in nanometer technologies are becoming important considerations for the design of cutting-edge FPGAs with millions of logic gates. As device features scale down, FPGA complexity per area increases while process variations induce large differences in performance amongst chips. As a result, it is becoming increasingly difficult to design FPGAs in a timely fashion or with reasonable yield. However, using trace-based timing and leakage modeling with process variations, these challenges can be overcome.

INNOVATION:  The invention uses trace-based timing and leakage modeling with process variations and allows for better optimization of FPGA designs in less time. The models are used to accurately abstract FPGA performance to a higher level. In this way, simulation time is reduced as fewer calculations are required per FPGA simulation. Moreover, the models take as inputs process parameters and their distributions. In this way, key process parameters, such as doping concentration or oxide thickness, may be tuned to allow for optimum FPGA performance. The models have been used to improve FPGA performance by as much as 73% compared to baseline designs that use standard design tools and methods.

POTENTIAL APPLICATIONS 

• FPGA and ASIC design

ADVANTAGES

• Improved FPGA performance
• Reduced FPGA power consumption for a given level of FPGA performance
• Improved yield resulting from tighter performance distribution

DEVELOPMENT-TO-DATE:  The invention has been implemented in software and verified by detailed simulation.

Reference: UCLA Case No. 2005-766

PCT Application: WO/07/005724