BACKGROUND:  Aggressive scaling of VLSI circuits makes interconnects the performance bottleneck, and buffer insertion is used extensively to reduce interconnect delay at the expense of more power dissipation. Interconnect optimization is a critical component of typical VLSI design flows for timing closure.

INNOVATION:  The invention has an innovative concept of applying dual-V_dd inside a routing tree, including buffer insertion for given tree topology and buffered tree. An algorithm to tackle the power-optimal buffer insertion and buffered routing tree construction problems using dual V_dd buffers is also disclosed. The algorithm improves on the current state of the art by using three speed-up techniques to obtain an effectively linear time algorithm.

POTENTIAL APPLICATIONS 

• Complex VLSI circuit design
• Power minimization within Dual V_dd buffer circuitry

ADVANTAGES

• 17x speed up (without implementation of fast algorithms) with little loss of optimality compared to current methods
• Dual-V_dd buffers reduce power by 23% at the minimum delay specification compared to buffer insertion with single V_dd buffers
• Compared to the delay-optimal tree using single V_dd buffers, the power-optimal buffered tree designed at UCLA reduces power by 7% (single V_dd buffers) and 18% (dual V_dd) buffers at the minimum delay specification
• By implementing fast algorithms, 50x and 100x speedup are obtained compared to the most efficient existing algorithms for dual V_dd buffer insertion and buffered tree construction respectively

DEVELOPMENT-TO-DATE:  The invention has been experimentally verified.

Reference: UCLA Case No. 2005-733

PCT Application: WO/06/135780