BACKGROUND:  Monolithic encapsulation of microstructures on wafer can reduce the final costs by protecting the delicate structures in a sealed cavity and so allowing use of the post-process packaging procedures regular electronic chip commonly use. Known monolithic encapsulation processes include lithographically making etching holes through the shell layer, but this leads to unintentional penetration of sealing materials which affect the encapsulated device. Long etch times can be required, which degrades the device and its characteristics. Another known monolithic encapsulation process uses a very thin permeable shell layer, which is too thin to serve as a freestanding structure, requiring a separate, thick reinforcement layer. All the known methods use polycrystalline silicon as the shell material and require high temperature processes.

INNOVATION:  The novel on-chip packaging provides encapsulation of typical surface-micromachined structures and devices inside monolithically formed microcavity without the need for separate etching holes, long etch times, or a reinforcement shell layer. Further, it prevents the penetration of sealing material into the device cavity, ensuring the proper function of devices, including nano-gap devices. It can even be performed in near room temperature. The invention is compatible with typical surface micromachining processes including polysilicon and metal structures.

POTENTIAL APPLICATIONS 

• On-chip packaging of MEMS devices.
• Vacuum packaging in micro sealed cavities.
• Self-closing microchannels.
• Implantable biosensors.
• Microseives & micropumps.

ADVANTAGES

• Encapsulates and seals MEMS microstructures and devices.
• Utilizes typical, well-established surface micromachining processes.
• Enables low/room temperature encapsulation processes.
• Provides a novel construction technique for various types of MEMS devices.

DEVELOPMENT-TO-DATE:  The technique has been successfully tested and confirmed.

Reference: UCLA Case No. 2005-689

US Application: 2006/0273065