BACKGROUND:  Although the internal clock frequency of CMOS chips is at over a few tens of GHz due to the technology scaling; however, the off-chip I/O signaling speed has been scaling much more slowly. The CMOS high-speed serial links already entered multi-Gb/s/pin speeds by using point-to-point connections, but the speed of parallel multi-drop or multi-point bus (e.g. memory interfaces) is still in less than 2 Gb/s/pin due to the signal integrity issues in the bandwidth-limited printed circuit board (PCB) environment. Moreover, the signaling power consumption is of increasing concern. Therefore, integrating a large number of high-speed I/Os on a single chip becomes extremely challenging due to excessive complexity and power consumption.

INNOVATION:  A new capacitive coupled pulsed signaling bus interface (CCBI) has been developed as an effective solution to reduce the I/O signaling power and improve the signal integrity in low-cost multi-point or multi-drop or point-to-point parallel bus systems. Single ended or differential synchronous pulsed signaling I/O technology utilizing on-chip capacitive coupling for low power, high bandwidth, parallel bus links (such as a system bus or a main memory bus) has been proposed.

To achieve the low power and high signal integrity in a multi-point bus, two key circuit techniques are employed. First, the pulsed signaling transceiver reduces the I/O power by treating the DC value of signals as redundant and using a diamond data eye. Second, capacitive coupling using on-chip metal-insulator-metal (MIM) capacitors enables a fully AC coupled multipoint bus, which minimizes the impedance discontinuities of a shared bus.

DEVELOPMENT-TO-DATE:  The circuit techniques are developed that reduce the I/O signaling power by a factor of 7.5 and increase the available channel bandwidth of a multi-point bus by a factor of 2 compared to the most recent memory bus I/O schemes. The demonstration chip is made, which incorporates differential bidirectional pulsed signaling, achieves 1 Gb/s over 10-cm printed circuit board traces with 2.9 mW of power for the driver and channel termination and 2.7 mW for the receiver pre-amplifier. Moreover, this I/O scheme uses conventional packaging and board technologies, which is suitable for low-cost high-density front-side buses or memory buses.

ABOUT THE LAB:  This and other developments in the Embedded Security can be found at the UCLA Embedded Security Group in the Electrical Engineering Department of UCLA, http://www.emsec.ee.ucla.edu

Reference: UCLA Case No. 2005-352

US Patent Application: 20060290377