BACKGROUND:  Advanced Encryption Standard (AES) is the most recent secret-key encryption standard which is accepted by the National Institute of Standards and Technology (NIST), and is used in different security applications. High throughput data encryption is essential in the networking applications that require secure data transmission at over 20 Gbps throughput rate, e.g. optical networks. For example, in one application the optical switches require cryptographically secure random numbers to generate the encrypted stream of data. For this purpose, the Advanced Encryption Standard algorithm designed for over 20 Gbps throughput is required to generate the sequences of random numbers.

INNOVATION:  A fully pipelined AES encryption processor is developed that can fit on a single chip FPGA. A 21.54 Gbits/s throughput is achieved using 84 Block RAMs and 5177 Slices of a VirtexII-Pro FPGA with a latency of 31 cycles and throughput per area rate of 4.2 Mbps/Slice. The original contribution consists of combining the pipelining techniques with a composite field implementation of the byte substitution phase of the AES algorithm.

POTENTIAL APPLICATIONS 

• Data encryption for optical network
• Data encryption for 10 Gbit ethernet

ADVANTAGES

1. The modification is a technically feasible and systematic modification to what is currently available; and,
2. The approach is flexible to accommodate any silencing gene candidates.

DEVELOPMENT-TO-DATE:  The fully synthesizable Verilog source code of this high speed AES encryption processor is developed. It is simulated using the Modelsim Tool and is synthesized using Synplicity synthesis tool.

ABOUT THE LAB:  This and other developments in Embedded Security can be found at the UCLA Embedded Security Group in the Electrical Engineering Department of UCLA, http://www.emsec.ee.ucla.edu

Reference: UCLA Case No. 2005-175