BACKGROUND:  Silicon on insulator (SOI) made of an insulating silicon dioxide layer in between two single-crystal silicon layers is an attractive way to improve the efficiency of semiconductor devices such as a transistor or MOSFET. MOSFETs fabricated on a SOI substrate can be classified as fully depleted SOI having a relatively thin SOI layer or partially depleted SOI having a relatively thick SOI layer. A thinner layer can suppress leakage current between the source and drain, but is characterized by a higher parasitic resistance. Thus, the fully depleted SOI is advantageous for logic circuits but not for high-power circuit configurations and a partially depleted SOI is suitable for high-power circuit configurations but now for a logic circuit. The trend in the semi-conductor industry is towards higher packing density and multi-functionality of semi-conductor devices, creating a demand for mixed loading circuits, where a hybrid substrate having a SOI layer with partially different thicknesses can support different types of devices on a single chip.

INNOVATION:  Using a simple fabrication process, the invention allows for control, through conventional lithography and etching steps, over the formation of the insulating layer of a SOI substrate. This novel and simple process gives the user a high degree of control over the thickness of the SOI layers as well as three-dimensional patterning of the insulating layer of the SOI substrate.

POTENTIAL APPLICATIONS: The invention is a key component to produce mixed loading circuits, where devices requiring opposing design parameters can be integrated onto a single chip, for applications in electronic devices.

ADVANTAGES

• Ability to fabricate SOI substrates with partially different thicknesses within a same layer
• Compatible with conventional CMOS fabrication steps
• The SOI layers can be formed to demonstrate complex topographies in three dimensions to accommodate complex circuit designs
• Provides a substrate for mixed loading circuits where fully depleted and partially depleted SOI is required to incorporated mixed components onto a single chip

DEVELOPMENT-TO-DATE:  Prototype silica films with 15nm pitch and 10nm diameter pores oriented vertically can be produced using cubic titania as a substrate.

Reference: UCLA Case No. 2004-328