CONSTANT POWER DESIGN ENCRYPTION TECHNOLOGY
UCLA Technology Available For Licensing

UCLA researchers in the Department of Electrical Engineering have developed, reduced-to-practice and characterized a CMOS logic architecture that will prevent information leakage of mission critical data.

BACKGROUND:  Electronic commerce, electronic banking and private networks cannot operate without a secure encryption technology. Many encryption algorithms have been developed and while secure against mathematical attacks are vulnerable to so called side-attacks. Side attacks can reveal the secret keys through information leaked by the hardware. Differential Power Analysis (DPA) is based on the fact that logic operations have power characteristics that depend on the input data. Statistical analysis of measured power traces link the switching activities of the circuit to the secret keys. Different techniques have been proposed to prevent this information leakage: interleaved dummy instructions, random power consumption, duplicate logic, etc.; however, all of these methods have eventually been circumvented.

Side-channel information is leaked due to the fact that logic operations charge and discharge total nodal capacitance depending on the exact operation.

INNOVATION:  A logic style has been invented with the unique property of charging in every cycle a total capacitance with a constant value independent of input. This innovative technology is called Sense Amplifier Based Logic (SABL). SABL remaps conventional logic building blocks in a fashion that connect all the internal nodes and their respective capacitances. Thus for each cycle every node is charged and discharged yielding an input-independent power consumption circuit. The input-independent power consumption makes this technology immune to differential power analysis.

DEVELOPMENT TO DATE:  The input-independent logic architecture has been fully characterized through simulation (0.18um CMOS process). The results validate the greatly reduced power variation relative to standard CMOS logic. The energy dissipation variation is reduced by up to 116 times relative to standard CMOS.

Reference: UCLA Case No. 2003-442 US Patent Application: 10/565,551

For additional technical details and current licensing
availability, please contact the following UCLA office:

UCLA Office of Intellectual Property
11000 Kinross Avenue, Suite #200
Los Angeles, CA 90095-7231
Tel: 310-794-0558 Fax: 310-794-0638
email: ncd@research.ucla.edu
NCD URL:   http://www.research.ucla.edu/tech/ucla03-442.htm

Lead Inventor: Ingrid Verbauwhede

UCLA Technologies Available for Licensing
http://www.research.ucla.edu/tech

Copyright © 2003 The Regents of the University of California.

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